Typical DRAM circuits include arrays of memory cells arranged in rows and columns. Each of the rows and columns are driven by a respective row decoder and column decoder. Typically, these memory circuits include several redundant rows and columns that are used as substitutes for defective locations in the memory array.
In the manufacture of integrated circuitry, redundant circuit elements are typically provided in the event not all of the circuitry or components prove operable upon testing. Thus, if some portion of the circuitry is inoperable, backup circuitry is available for proper operation of the integrated circuit. One manner of providing for such circuit redundancy may be achieved via antifuses and redundant circuit logic for activating such antifuses. An antifuse is a component which upon activation or “blowing” creates a short between two conductive elements.
Traditionally, the fuses have been blown by having a laser cut the fuse conductors to remove the conductive paths through the fuses. One problem with such an approach is that the laser cutting of the fuses is time consuming, difficult and imprecise. Therefore, the cost and reliability of memory devices employing laser fuse bank circuits can be less than satisfactory.
More recently, memory devices have been employing antifuse banks in place of conventional fuses. Antifuses are capacitive-type structures that, in their unblown states, form open circuits. Antifuses may be blown by applying a high voltage across the antifuse. The high voltage causes the capacitive-type structure to break down, forming a conductive path through the antifuse. Therefore, blown antifuses conduct and unblown antifuses do not conduct.
Antifuses are similar in construction to capacitors, as evidenced by FIG. 1. There illustrated are portions of a semiconductor wafer 100 in process. The left or “A” portion of the FIG. 1 illustrates a capacitor construction, whereas the right or “B” portion illustrates an antifuse. More specifically, wafer fragment 100 is comprised of a bulk substrate 102, diffusion regions 104 and 106 and field oxide regions 108. An insulator layer 120 is provided over substrate 102, with contacts 122 and 124 being provided therethrough to diffusion regions 104 and 106, respectively. Referring specifically to the capacitor construction of the “A” portion, such is comprised of a patterned electrically conductive storage node 126, an intervening dielectric layer 128, and an overlying capacitor cell layer 130. Referring to the antifuse “B” side of FIG. 1, such is comprised of a lower conductive inner antifuse plate 130 and an outer antifuse plate 132. These are separated and electrically isolated from one another by an intervening antifuse dielectric element 134. Accordingly, a capacitor and antifuse are similar to one another in that two conductive elements are separated by dielectric material.
To “blow” the antifuse, a certain level of quanta of charge is passed through fuse dielectric 134 to cause a physical breakdown of intervening dielectric element 134. Such creates permanent electrically conductive paths between elements 132 and 130, thus forming a desired electrically conductive short. While redundant repair is one goal associated with the blowing of antifuses, as is known in the art, antifuses may be blown e.g., to change the state of another signal associated with a bad column, or to lessen defect currents, etc. Further details regarding antifuse and capacitor construction is shown in U.S. Pat. No. 6,291,871, commonly assigned to the assignee of this application, the entire contents of which are incorporated herein by reference.
FIG. 2 illustrates in cross-section exemplary DRAM circuitry 200. For purposes of illustration, a single memory cell of an array using typical bit line circuitry is shown. Reference numeral 206 refers to a masking step wherein typical polysilicon contacting openings are created for the initial poly plugs to a source/drain region which connects to the capacitor side. Bit lines 210 are thereafter fabricated. Reference numeral 208 refers to the mask step for creating another set of mask openings which connect with plugs (e.g., 206) for connecting with individual storage nodes of respective capacitors 203.
A memory cell of DRAM circuitry constitutes a word line having a pair of source/drain regions. One of the source/drain regions connects to a bit line. The other of the source/drain regions connects to a capacitor. More specifically, the direct connection to the capacitor from the source/drain region is to one of the electrodes of the capacitor, commonly called a storage node of an individual capacitor. The opposing plate of the capacitor is referred to as a cell plate. The cell plates of all the capacitors in a sub-array of a DRAM circuit are all connected together and provided at the same potential (e.g., Vcc/2, commonly referred to as “DVC2”).
Peripheral circuitry of the DRAM circuitry 200 is identified with reference numeral 202. The illustrated contact openings show a typical prior art problem in establishing current connection to the cell plate layer as well as to circuitry in the periphery. Depth of etch “d1” to the peripheral circuitry 202 is considerably greater than depth of etch “d2” to the cell plate layer 204 in the sub-array. Such variation creates fabrication problems when etching is performed to different depth layers using the same mask. During the performance of such etching using a single mask, one may encounter cell plates prior to reaching the peripheral circuitry and thereby posing a risk of punching through the cell plate layer and shorting to underlying circuitry.
It would be desirable to overcome the above-identified problems.